| 1 |
2072 |
malin |
/*
|
| 2 |
|
|
* File: sl1reg.h
|
| 3 |
|
|
*
|
| 4 |
|
|
* Copyright (c) 2006 Beijing SimpLight Nanoelectornics, Ltd.
|
| 5 |
|
|
* All rights reserved.
|
| 6 |
|
|
*
|
| 7 |
|
|
* Redistribution and use in source and binary forms, with or without modification,
|
| 8 |
|
|
* are permitted provided that the following conditions are met:
|
| 9 |
|
|
*
|
| 10 |
|
|
* 1.Redistributions of source code must retain the above copyright notice,
|
| 11 |
|
|
* this list of conditions and the following disclaimer.
|
| 12 |
|
|
* 2.Redistributions in binary form must reproduce the above copyright notice,
|
| 13 |
|
|
* this list of conditions and the following disclaimer in the documentation
|
| 14 |
|
|
* and/or other materials provided with the distribution.
|
| 15 |
|
|
*
|
| 16 |
|
|
* THIS SOFTWARE IS PROVIDED BY THE FREEBSD PROJECT ``AS IS'' AND ANY EXPRESS
|
| 17 |
|
|
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
| 18 |
|
|
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
| 19 |
|
|
* IN NO EVENT SHALL THE FREEBSD PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
| 20 |
|
|
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
| 21 |
|
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
| 22 |
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
| 23 |
|
|
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
| 24 |
|
|
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
| 25 |
|
|
* OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 26 |
|
|
*/
|
| 27 |
|
|
|
| 28 |
|
|
#ifndef SL1REG_H_
|
| 29 |
|
|
#define SL1REG_H_
|
| 30 |
|
|
|
| 31 |
|
|
#include "defs.h"
|
| 32 |
|
|
#include "breg.h"
|
| 33 |
|
|
#include "sl1regdefs.h"
|
| 34 |
|
|
#include "status.h"
|
| 35 |
|
|
#include "sl1defs.h"
|
| 36 |
|
|
|
| 37 |
|
|
#define GET_ACC_40BIT(data) ((data<<24)>>24)
|
| 38 |
|
|
|
| 39 |
|
|
class SL1Instr;
|
| 40 |
|
|
|
| 41 |
|
|
class SL1Register : public BaseRegister<SL1Instr> {
|
| 42 |
|
|
|
| 43 |
|
|
private:
|
| 44 |
|
|
WORD _gpr[REG_GPR_SIZE];
|
| 45 |
|
|
WORD _ja;
|
| 46 |
|
|
WORD _ra;
|
| 47 |
|
|
|
| 48 |
|
|
UWORD _loop_cnt[REG_LOOP_CUR_SIZE];
|
| 49 |
|
|
ADDR _loopStartPC[REG_LOOP_CUR_SIZE];
|
| 50 |
|
|
ADDR _loopEndPC[REG_LOOP_CUR_SIZE];
|
| 51 |
|
|
UINT _loopExecCnt[REG_LOOP_CUR_SIZE];
|
| 52 |
|
|
|
| 53 |
|
|
WORD _ar[REG_AR_CUR_SIZE];
|
| 54 |
|
|
WORD _ar_usize[REG_AR_CUR_SIZE];
|
| 55 |
|
|
DWORD _acc[REG_ACC_CUR_SIZE];
|
| 56 |
|
|
WORD _hi;
|
| 57 |
|
|
WORD _ffe_fft;
|
| 58 |
|
|
WORD _ffe_viterbi;
|
| 59 |
|
|
WORD _ffe_trback;
|
| 60 |
|
|
WORD _statusReg;
|
| 61 |
|
|
|
| 62 |
|
|
public:
|
| 63 |
|
|
SL1Register(ProcessStatus<SL1Instr>& status, UINT thid);
|
| 64 |
|
|
|
| 65 |
|
|
INT createNameMap(RegMap& regmap); // create register name map and return map size
|
| 66 |
|
|
char* getRegName(UINT32 index, UINT32 regbase);
|
| 67 |
|
|
char* getRegName(UINT32 norm_index);
|
| 68 |
|
|
|
| 69 |
|
|
void clear();
|
| 70 |
|
|
void clearFEReg();
|
| 71 |
|
|
|
| 72 |
|
|
WORD getSP(void){
|
| 73 |
|
|
return _gpr[INDEX_REG_SP];
|
| 74 |
|
|
}
|
| 75 |
|
|
|
| 76 |
|
|
WORD getGPR(UINT32 index) {
|
| 77 |
|
|
AppFatal((index<REG_GPR_SIZE), ("Register: invalid gpr index (%d) @0x%08x.", index, status().pre_pc()));
|
| 78 |
|
|
return _gpr[index];
|
| 79 |
|
|
}
|
| 80 |
|
|
|
| 81 |
|
|
void setGPR(UINT32 index, WORD data) {
|
| 82 |
|
|
if(index==0){
|
| 83 |
|
|
data = 0;
|
| 84 |
|
|
}
|
| 85 |
|
|
AppFatal((index<REG_GPR_SIZE), ("Register: invalid gpr index (%d) @0x%08x.", index, status().pre_pc()));
|
| 86 |
|
|
_gpr[index] = data;
|
| 87 |
|
|
}
|
| 88 |
|
|
|
| 89 |
|
|
void setSP(WORD data){
|
| 90 |
|
|
_gpr[INDEX_REG_SP] = data;
|
| 91 |
|
|
}
|
| 92 |
|
|
|
| 93 |
|
|
WORD getStatusReg(void) { return _statusReg; }
|
| 94 |
|
|
void setStatusReg(WORD s) { _statusReg = s; }
|
| 95 |
|
|
|
| 96 |
|
|
WORD getRA(void) {
|
| 97 |
|
|
return _ra;
|
| 98 |
|
|
}
|
| 99 |
|
|
void setRA(WORD data) {
|
| 100 |
|
|
_ra = data;
|
| 101 |
|
|
}
|
| 102 |
|
|
WORD getJA(void) {
|
| 103 |
|
|
return _ja;
|
| 104 |
|
|
}
|
| 105 |
|
|
void setJA(WORD data) {
|
| 106 |
|
|
_ja = data;
|
| 107 |
|
|
}
|
| 108 |
|
|
UWORD getLOOP_CNT(UINT32 index) {
|
| 109 |
|
|
AppFatal((index<REG_LOOP_CUR_SIZE), ("Register: invalid loop cnt index (%d) @0x%08x.", index, status().pre_pc()));
|
| 110 |
|
|
return _loop_cnt[index];
|
| 111 |
|
|
}
|
| 112 |
|
|
void setLOOP_CNT(UINT32 index, UWORD data) {
|
| 113 |
|
|
AppFatal((index<REG_LOOP_CUR_SIZE), ("Register: invalid loop cnt index (%d) @0x%08x.", index, status().pre_pc()));
|
| 114 |
|
|
_loop_cnt[index] = data;
|
| 115 |
|
|
}
|
| 116 |
|
|
|
| 117 |
|
|
/*for loop in cexec.h */
|
| 118 |
|
|
void pushExecCnt(UINT cnt)
|
| 119 |
|
|
{
|
| 120 |
|
|
AppFatal((_loopExecCnt[REG_LOOP_CUR_SIZE-1]==0),("Register: too much nested loop @0x%08x.", status().pre_pc()));
|
| 121 |
|
|
int i;
|
| 122 |
|
|
for(i=REG_LOOP_CUR_SIZE-1;i>0;i--)
|
| 123 |
|
|
_loopExecCnt[i] = _loopExecCnt[i-1];
|
| 124 |
|
|
_loopExecCnt[0] = cnt;
|
| 125 |
|
|
}
|
| 126 |
|
|
|
| 127 |
|
|
void popExecCnt(void)
|
| 128 |
|
|
{
|
| 129 |
|
|
int i;
|
| 130 |
|
|
for(i=0;i<REG_LOOP_CUR_SIZE-1;i++)
|
| 131 |
|
|
_loopExecCnt[i] = _loopExecCnt[i+1];
|
| 132 |
|
|
_loopExecCnt[REG_LOOP_CUR_SIZE-1] = 0;
|
| 133 |
|
|
}
|
| 134 |
|
|
|
| 135 |
|
|
UINT loopExecCntLv0(void){
|
| 136 |
|
|
return _loopExecCnt[0];
|
| 137 |
|
|
}
|
| 138 |
|
|
|
| 139 |
|
|
void loopExecCntLv0(UINT cnt)
|
| 140 |
|
|
{
|
| 141 |
|
|
_loopExecCnt[0]=cnt;
|
| 142 |
|
|
}
|
| 143 |
|
|
|
| 144 |
|
|
void pushStartPC(ADDR loopStart)
|
| 145 |
|
|
{
|
| 146 |
|
|
AppFatal((_loopStartPC[REG_LOOP_CUR_SIZE-1]==0),("Register: too much nested loop @0x%08x.", status().pre_pc()));
|
| 147 |
|
|
int i;
|
| 148 |
|
|
for(i=REG_LOOP_CUR_SIZE-1;i>0;i--)
|
| 149 |
|
|
_loopStartPC[i] = _loopStartPC[i-1];
|
| 150 |
|
|
_loopStartPC[0] = loopStart;
|
| 151 |
|
|
}
|
| 152 |
|
|
|
| 153 |
|
|
void popStartPC(void)
|
| 154 |
|
|
{
|
| 155 |
|
|
int i;
|
| 156 |
|
|
for(i=0;i<REG_LOOP_CUR_SIZE-1;i++)
|
| 157 |
|
|
_loopStartPC[i] = _loopStartPC[i+1];
|
| 158 |
|
|
_loopStartPC[REG_LOOP_CUR_SIZE-1] = 0;
|
| 159 |
|
|
}
|
| 160 |
|
|
|
| 161 |
|
|
ADDR loopStartPCLv0(void) {
|
| 162 |
|
|
return _loopStartPC[0];
|
| 163 |
|
|
}
|
| 164 |
|
|
|
| 165 |
|
|
void pushEndPC(ADDR endPC)
|
| 166 |
|
|
{
|
| 167 |
|
|
AppFatal((_loopEndPC[REG_LOOP_CUR_SIZE-1]==0),("Register: too much nested loop @0x%08x.", status().pre_pc()));
|
| 168 |
|
|
int i;
|
| 169 |
|
|
for(i=REG_LOOP_CUR_SIZE-1;i>0;i--)
|
| 170 |
|
|
_loopEndPC[i] = _loopEndPC[i-1];
|
| 171 |
|
|
_loopEndPC[0] = endPC;
|
| 172 |
|
|
}
|
| 173 |
|
|
|
| 174 |
|
|
void popEndPC(void)
|
| 175 |
|
|
{
|
| 176 |
|
|
int i;
|
| 177 |
|
|
for(i=0;i<REG_LOOP_CUR_SIZE-1;i++)
|
| 178 |
|
|
_loopEndPC[i] = _loopEndPC[i+1];
|
| 179 |
|
|
_loopEndPC[REG_LOOP_CUR_SIZE-1] = 0;
|
| 180 |
|
|
}
|
| 181 |
|
|
|
| 182 |
|
|
ADDR loopEndPCLv0(void) {
|
| 183 |
|
|
return _loopEndPC[0];
|
| 184 |
|
|
}
|
| 185 |
|
|
|
| 186 |
|
|
UINT loopExecCnt(INT index){
|
| 187 |
|
|
AppFatal((index<REG_LOOP_CUR_SIZE), ("Exec: Invalid loop index (%d)", index));
|
| 188 |
|
|
return _loopExecCnt[index];
|
| 189 |
|
|
}
|
| 190 |
|
|
|
| 191 |
|
|
void loopExecCnt(INT index,UINT count) {
|
| 192 |
|
|
AppFatal((index<REG_LOOP_CUR_SIZE), ("Exec: Invalid loop index (%d)", index));
|
| 193 |
|
|
_loopExecCnt[index] = count;
|
| 194 |
|
|
}
|
| 195 |
|
|
ADDR loopStartPC(UINT index) {
|
| 196 |
|
|
AppFatal((index<REG_LOOP_CUR_SIZE), ("Exec: Invalid loop index (%d)", index));
|
| 197 |
|
|
return _loopStartPC[index];
|
| 198 |
|
|
}
|
| 199 |
|
|
|
| 200 |
|
|
void loopStartPC(UINT index,ADDR addr) {
|
| 201 |
|
|
AppFatal((index<REG_LOOP_CUR_SIZE), ("Exec: Invalid loop index (%d)", index));
|
| 202 |
|
|
_loopStartPC[index] = addr;
|
| 203 |
|
|
}
|
| 204 |
|
|
|
| 205 |
|
|
ADDR loopEndPC(UINT index) {
|
| 206 |
|
|
AppFatal((index<REG_LOOP_CUR_SIZE), ("Exec: Invalid loop index (%d)", index));
|
| 207 |
|
|
return _loopEndPC[index];
|
| 208 |
|
|
}
|
| 209 |
|
|
|
| 210 |
|
|
void loopEndPC(UINT index,ADDR addr) {
|
| 211 |
|
|
AppFatal((index<REG_LOOP_CUR_SIZE), ("Exec: Invalid loop index (%d)", index));
|
| 212 |
|
|
_loopEndPC[index] = addr;
|
| 213 |
|
|
}
|
| 214 |
|
|
|
| 215 |
|
|
WORD getFEReg(UINT32 index) {
|
| 216 |
|
|
AppFatal((index<EBASE_FE_REGS_SIZE), ("Register: invalid FE reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 217 |
|
|
if(index>=0&&index<REG_LOOP_CUR_SIZE) {
|
| 218 |
|
|
return loopExecCnt(index);
|
| 219 |
|
|
}
|
| 220 |
|
|
else if(index>=REG_LOOP_CUR_SIZE&&index<(REG_LOOP_CUR_SIZE*2)) {
|
| 221 |
|
|
return loopStartPC(index-REG_LOOP_CUR_SIZE);
|
| 222 |
|
|
}
|
| 223 |
|
|
else if(index>=(REG_LOOP_CUR_SIZE*2)&&index<=EBASE_FE_REGS_SIZE-1) {
|
| 224 |
|
|
return loopEndPC(index-(REG_LOOP_CUR_SIZE*2));
|
| 225 |
|
|
}
|
| 226 |
|
|
//else if(index==EBASE_FE_REGS_SIZE-1) {
|
| 227 |
|
|
// return loopCurIndex();
|
| 228 |
|
|
//}
|
| 229 |
|
|
else {
|
| 230 |
|
|
AppFatal((0), ("Register: invalid FE reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 231 |
|
|
}
|
| 232 |
|
|
return -1;
|
| 233 |
|
|
}
|
| 234 |
|
|
|
| 235 |
|
|
WORD getCTRL(UINT32 index) {
|
| 236 |
|
|
AppFatal((index<REG_ALL_CTRL_SIZE), ("Register: invalid ctrl reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 237 |
|
|
if(index==ECR_JA ) {
|
| 238 |
|
|
return getJA();
|
| 239 |
|
|
}
|
| 240 |
|
|
else if(index==ECR_RA ) {
|
| 241 |
|
|
return getRA();
|
| 242 |
|
|
}
|
| 243 |
|
|
else if(index>=ECR_LOOP_CNT&&index<ECR_INSTR_CNT) {
|
| 244 |
|
|
return getLOOP_CNT(index-ECR_LOOP_CNT);
|
| 245 |
|
|
}
|
| 246 |
|
|
else {
|
| 247 |
|
|
AppFatal((0), ("Register: invalid ctrl reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 248 |
|
|
}
|
| 249 |
|
|
return -1;
|
| 250 |
|
|
}
|
| 251 |
|
|
|
| 252 |
|
|
void setCTRL(UINT32 index, WORD data) {
|
| 253 |
|
|
AppFatal((index<REG_ALL_CTRL_SIZE), ("Register: invalid ctrl reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 254 |
|
|
if(index==ECR_JA ) {
|
| 255 |
|
|
setJA(data);
|
| 256 |
|
|
}
|
| 257 |
|
|
else if(index==ECR_RA ) {
|
| 258 |
|
|
setRA(data);
|
| 259 |
|
|
}
|
| 260 |
|
|
else if(index>=ECR_LOOP_CNT&&index<ECR_INSTR_CNT) {
|
| 261 |
|
|
setLOOP_CNT(index-ECR_LOOP_CNT, data);
|
| 262 |
|
|
}
|
| 263 |
|
|
else {
|
| 264 |
|
|
AppFatal((0), ("Register: invalid ctrl reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 265 |
|
|
}
|
| 266 |
|
|
}
|
| 267 |
|
|
|
| 268 |
|
|
WORD getGPR16(UINT32 index) {
|
| 269 |
|
|
AppFatal((index<REG_GPR_SIZE), ("Register: invalid gpr index (%d) @0x%08x.", index, status().pre_pc()));
|
| 270 |
|
|
INT16 tmp = _gpr[index];
|
| 271 |
|
|
return ((WORD)tmp);
|
| 272 |
|
|
}
|
| 273 |
|
|
void setGPR16(UINT32 index, WORD data) {
|
| 274 |
|
|
if(index==0){
|
| 275 |
|
|
data = 0;
|
| 276 |
|
|
}
|
| 277 |
|
|
AppFatal((index<REG_GPR_SIZE), ("Register: invalid gpr index (%d) @0x%08x.", index, status().pre_pc()));
|
| 278 |
|
|
data &= HWORD_DATA_MASK;
|
| 279 |
|
|
_gpr[index] = data;
|
| 280 |
|
|
}
|
| 281 |
|
|
|
| 282 |
|
|
//BB ctrl regs
|
| 283 |
|
|
WORD getHI(void) {
|
| 284 |
|
|
return _hi;
|
| 285 |
|
|
}
|
| 286 |
|
|
void setHI(WORD data) {
|
| 287 |
|
|
_hi = data;
|
| 288 |
|
|
}
|
| 289 |
|
|
|
| 290 |
|
|
DWORD getACC(UINT32 index) {
|
| 291 |
|
|
AppFatal((index<REG_ACC_CUR_SIZE), ("Register: invalid acc index (%d) @0x%08x.", index, status().pre_pc()));
|
| 292 |
|
|
return _acc[index];
|
| 293 |
|
|
}
|
| 294 |
|
|
void setACC(UINT32 index, DWORD data) {
|
| 295 |
|
|
AppFatal((index<REG_ACC_CUR_SIZE), ("Register: invalid acc index (%d) @0x%08x.", index, status().pre_pc()));
|
| 296 |
|
|
data = GET_ACC_40BIT(data);
|
| 297 |
|
|
_acc[index] = data;
|
| 298 |
|
|
}
|
| 299 |
|
|
UWORD getAR(UINT32 index) {
|
| 300 |
|
|
AppFatal((index<REG_AR_CUR_SIZE), ("Register: invalid ar index (%d) @0x%08x.", index, status().pre_pc()));
|
| 301 |
|
|
return (_ar[index]);
|
| 302 |
|
|
}
|
| 303 |
|
|
void setAR(UINT32 index, UWORD data) {
|
| 304 |
|
|
AppFatal((index<REG_AR_CUR_SIZE), ("Register: invalid ar index (%d) @0x%08x.", index, status().pre_pc()));
|
| 305 |
|
|
_ar[index] = data;
|
| 306 |
|
|
}
|
| 307 |
|
|
WORD getAR_USIZE(UINT32 index) {
|
| 308 |
|
|
AppFatal((index<REG_AR_CUR_SIZE), ("Register: invalid ar_usize index (%d) @0x%08x.", index, status().pre_pc()));
|
| 309 |
|
|
return (_ar_usize[index]);
|
| 310 |
|
|
}
|
| 311 |
|
|
void setAR_USIZE(UINT32 index, UWORD data) {
|
| 312 |
|
|
AppFatal((index<REG_AR_CUR_SIZE), ("Register: invalid ar_usize index (%d) @0x%08x.", index, status().pre_pc()));
|
| 313 |
|
|
_ar_usize[index] = data;
|
| 314 |
|
|
}
|
| 315 |
|
|
void setFFE_FFT(WORD data){ _ffe_fft = data; }
|
| 316 |
|
|
WORD getFFE_FFT(void) { return _ffe_fft; }
|
| 317 |
|
|
|
| 318 |
|
|
void setFFE_VITERBI(WORD data){ _ffe_viterbi = data; }
|
| 319 |
|
|
WORD getFFE_VITERBI(void) { return _ffe_viterbi; }
|
| 320 |
|
|
|
| 321 |
|
|
void setFFE_TRBACK(WORD data){ _ffe_trback = data; }
|
| 322 |
|
|
WORD getFFE_TRBACK(void) { return _ffe_trback; }
|
| 323 |
|
|
|
| 324 |
|
|
void setSPEC(UINT32 index, DWORD data) {
|
| 325 |
|
|
AppFatal((index<REG_ALL_C3_SPEC_SIZE), ("Register: invalid spec reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 326 |
|
|
if(index==ESR_HI) {
|
| 327 |
|
|
setHI(data);
|
| 328 |
|
|
}
|
| 329 |
|
|
else if(index>=ESR_AR && index<(ESR_AR+REG_AR_CUR_SIZE)) {
|
| 330 |
|
|
_ar[index] = (WORD)data;
|
| 331 |
|
|
}
|
| 332 |
|
|
else if(index>=ESR_AR_USIZE &&index<(ESR_AR_USIZE+REG_AR_CUR_SIZE)) {
|
| 333 |
|
|
_ar_usize[index-ESR_AR_USIZE] = (WORD)data;
|
| 334 |
|
|
}
|
| 335 |
|
|
else if(index>=ESR_ACC &&index<ESR_HI) {
|
| 336 |
|
|
_acc[index-ESR_ACC] = data;
|
| 337 |
|
|
}
|
| 338 |
|
|
else if(index==ESR_FFT) {
|
| 339 |
|
|
_ffe_fft = data;
|
| 340 |
|
|
}
|
| 341 |
|
|
else if(index==ESR_VITERBI) {
|
| 342 |
|
|
_ffe_viterbi = data;
|
| 343 |
|
|
}
|
| 344 |
|
|
else if(index==ESR_TRBACK){
|
| 345 |
|
|
_ffe_trback = data;
|
| 346 |
|
|
}
|
| 347 |
|
|
else if(index==ESR_STATUS){
|
| 348 |
|
|
AppFatal((0), ("Register: status spec reg is read only", status().pre_pc()));
|
| 349 |
|
|
}
|
| 350 |
|
|
else {
|
| 351 |
|
|
AppFatal((0), ("Register: invalid spec reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 352 |
|
|
}
|
| 353 |
|
|
}
|
| 354 |
|
|
|
| 355 |
|
|
WORD getSPEC(UINT32 index) {
|
| 356 |
|
|
AppFatal((index<REG_ALL_C3_SPEC_SIZE), ("Register: invalid spec reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 357 |
|
|
if(index==ESR_HI) {
|
| 358 |
|
|
return getHI();
|
| 359 |
|
|
}
|
| 360 |
|
|
else if(index>=ESR_AR && index<(ESR_AR+REG_AR_CUR_SIZE)) {
|
| 361 |
|
|
return _ar[index];
|
| 362 |
|
|
}
|
| 363 |
|
|
else if(index>=ESR_AR_USIZE &&index<(ESR_AR_USIZE+REG_AR_CUR_SIZE)) {
|
| 364 |
|
|
return _ar_usize[index-ESR_AR_USIZE];
|
| 365 |
|
|
}
|
| 366 |
|
|
else if(index>=ESR_ACC &&index<ESR_HI) {
|
| 367 |
|
|
return _acc[index-ESR_ACC];
|
| 368 |
|
|
}
|
| 369 |
|
|
else if(index==ESR_FFT) {
|
| 370 |
|
|
return _ffe_fft;
|
| 371 |
|
|
}
|
| 372 |
|
|
else if(index==ESR_VITERBI) {
|
| 373 |
|
|
return _ffe_viterbi;
|
| 374 |
|
|
}
|
| 375 |
|
|
else if(index==ESR_TRBACK) {
|
| 376 |
|
|
return _ffe_trback;
|
| 377 |
|
|
}
|
| 378 |
|
|
else if(index==ESR_STATUS){
|
| 379 |
|
|
return _statusReg;
|
| 380 |
|
|
}
|
| 381 |
|
|
else {
|
| 382 |
|
|
AppFatal((0), ("Register: invalid spec reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 383 |
|
|
return ESR_UNDEF;
|
| 384 |
|
|
}
|
| 385 |
|
|
}
|
| 386 |
|
|
EREG_SPEC getSPECIndex(UINT32 index) {
|
| 387 |
|
|
AppFatal((index<REG_ALL_C3_SPEC_SIZE), ("Register: invalid spec reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 388 |
|
|
if(index>=ESR_AR &&index<(ESR_AR+REG_AR_CUR_SIZE)) {
|
| 389 |
|
|
return ESR_AR;
|
| 390 |
|
|
}
|
| 391 |
|
|
if(index>=ESR_AR_USIZE &&index<(ESR_AR_USIZE+REG_AR_CUR_SIZE)) {
|
| 392 |
|
|
return ESR_AR_USIZE;
|
| 393 |
|
|
}
|
| 394 |
|
|
else if(index>=ESR_ACC &&index<ESR_MAX) {
|
| 395 |
|
|
return ESR_ACC;
|
| 396 |
|
|
}
|
| 397 |
|
|
else if(index==ESR_HI) {
|
| 398 |
|
|
return ESR_HI;
|
| 399 |
|
|
}
|
| 400 |
|
|
else {
|
| 401 |
|
|
AppFatal((0), ("Register: invalid spec reg index (%d) @0x%08x.", index, status().pre_pc()));
|
| 402 |
|
|
return ESR_UNDEF;
|
| 403 |
|
|
}
|
| 404 |
|
|
}
|
| 405 |
|
|
|
| 406 |
|
|
INT getRegIndexByName(const STRING regName);
|
| 407 |
|
|
INT setRegByName(const STRING regName, const DWORD value);
|
| 408 |
|
|
INT getRegisterNames(char *buf, int len);
|
| 409 |
|
|
bool isValidRegName(const STRING regName);
|
| 410 |
|
|
void dumpRegs(FILE* out, const char* regSetName);
|
| 411 |
|
|
void dumpRegs2File(FILE* out, const char* regSetName);
|
| 412 |
|
|
INT initRegs(FILE *in, const char* regSetName);
|
| 413 |
|
|
};
|
| 414 |
|
|
|
| 415 |
|
|
const STRING reg_name_gpr[REG_GPR_SIZE] = {
|
| 416 |
|
|
"zero", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
| 417 |
|
|
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
|
| 418 |
|
|
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
|
| 419 |
|
|
"r24", "r25", "r26", "r27", "gp", "sp", "r30", "r31"
|
| 420 |
|
|
};
|
| 421 |
|
|
|
| 422 |
|
|
const STRING reg_name_ctrl[REG_ALL_CTRL_SIZE] = {
|
| 423 |
|
|
"ja", "ra",
|
| 424 |
|
|
"lcnt0", "lcnt1", "lcnt2", "lcnt3",
|
| 425 |
|
|
};
|
| 426 |
|
|
|
| 427 |
|
|
const STRING reg_name_fe[EBASE_FE_REGS_SIZE] = {
|
| 428 |
|
|
"felcnt0", "felcnt1", "felcnt2", "felcnt3",
|
| 429 |
|
|
"felstart0", "felstart1", "felstart2", "felstart3",
|
| 430 |
|
|
"felend0", "felend1", "felend2", "felend3",
|
| 431 |
|
|
};
|
| 432 |
|
|
|
| 433 |
|
|
const STRING reg_name_c3_spec[REG_ALL_C3_SPEC_SIZE] = {
|
| 434 |
|
|
"ar0", "ar1", "ar2", "ar3",
|
| 435 |
|
|
"ar4", "ar5", "ar6", "ar7",
|
| 436 |
|
|
"ar_usize0", "ar_usize1", "ar_usize2", "ar_usize3",
|
| 437 |
|
|
"ar_usize4", "ar_usize5", "ar_usize6", "ar_usize7",
|
| 438 |
|
|
"acc0", "acc1", "acc2", "acc3", "hi","ffe_fft","ffe_viterbi","ffe_trback","status",
|
| 439 |
|
|
};
|
| 440 |
|
|
|
| 441 |
|
|
#endif /*SL1REG_H_*/
|